TS4405P - single p-channel 1.8v specified microsurf? general description taiwan semiconductor?s new low cost, state of the art microsurf? lateral mosfet process technology in chipscale bondwireless packaging minimizes pcb space and r ds(on) plus provides an ultra- low qg x r ds(on) figure of merit. absolute maximum ratings t a =25c unless otherwise noted symbol parameter ratings units v dss drain-source voltage -12 v v gss gate-source voltage + 8v i d drain current ? continuous -4.9 a ? pulsed -10 p d power dissipation (steady state) 1.5 w t j , t stg operating and storage junction temperature range -55 to +150 oc thermal characteristics r ja thermal resistance, junction-to-ambient 85 c/w r jr thermal resistance, junction-to-ball 20 r jc thermal resistance, junction-to-case 1.8 microsurf? for load switching and pa switch patent pending features ? -4.9a, -12v r ds(on) =50m ? at -4.5 volts ? -4.4a, -12v r ds(on) =70m ? at -2.5 volts ? -4.0a, -12v r ds(on) = 90m ? at -1.8 volts ? low profile package: less than 0. 8mm height when mounted on pcb. ? occupies only 1.21 mm 2 of pcb area. less than 30% of the area of a sc-70. ? excellent thermal characteristics. ? lead free solder bumps available. preliminary data sheet for information only 1 6/8/03 rev0 bump side view ss g d
electrical characteristics t a =25c unless otherwise specified 2 6/8/03 rev0 symbol parameter test condition min typ max units v (bd)ss drain-source breakdow n voltage v gs =0v, i d =-250a -11 v i dss zero gate voltage drain current v ds =-12v, v gs =0v -1 a zero gate voltage drain current v ds =-12v, v gs =0v, t=70c -5 a i gss gate-body leakage v gs =8v, v ds =0v 100 na v gs(th) gate threshold voltage v ds =v gs , i d =-250a -0,58 v drain-source on-state resistance v gs =-4.5v, i d =-1a 50 m ? drain-source on-state resistance v gs =-2.5v, i d =-1a 70 m ? drain-source on-state resistance v gs =-1.8v, i d =-1a 90 m ? c is s input capacitance v ds =-12v, v g =0v, f=1mhz 300 pf c oss output capacitance v ds =-12v, v g =0v, f=1mhz 200 pf c rss reverse transfer capacitance v ds =-12v, v g =0v, f=1mhz 80 pf q g total gate charge v gs =-4.5v, i d =-4a, v ds =-8v 10 nc q gs gate source-charge v gs =-4.5v, i d =-4a, v ds =-8v 2 nc q gd gate drain-charge v gs =-4.5v, i d =-4a, v ds =-8v 1 nc v sd diode forw ard voltage i s =-4a, v gs =0v 0.7 v r ds(on) preliminary data sheet TS4405P
dimensional outline and pad layout 0.50mm 0.50mm ? 0.25mm solder mask ? ~ 0.35mm land pattern recommendation ss d g d = drain pad s = source pad g = gate pad silicon 0.80mm max 0.27mm 0.50mm 1.10mm 0.50mm 0.30mm 0.30mm bump ? 0.37mm 1.10mm 3 6/8/03 rev0 44xxx mark on backside of die xxx = date/lot traceability code bumps are eutectic solder 63/37 sn/pb preliminary data sheet TS4405P
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